HD6417751RBP240V Datasheet, PDF (599/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. Direct Memory Access Controller (DMAC)
• Channel 6 (SH7751R only): Single or dual address mode. External requests are
accepted.
• Channel 7 (SH7751R only): Single or dual address mode. External requests are
accepted.
• In DDT mode, data transfer is carried out by the SH7751 using the DBREQ, BAVL,
TR, TDACK, ID [1:0], and D[31:0] signals to perform handshaking between the
external device and the DMAC, and data transfer is carried out by the SH7751R using
the DBREQ, BAVL, TR, TDACK, ID [2:0], and D[31:0] signals to perform
handshaking between the external device and the DMAC.
• Request-queue clear for each channel (SH7751R only)
Request queues can be cleared on a channel-by-channel basis in either of the following
two ways.
⎯ Clearing a request queue by DTR format
The request queues of the relevant channel are cleared when it receives DTR.SZ =
110, DTR.ID = 00, DTR.MD = 11, and DTR.COUNT [7:4]* = [1–8].
⎯ Using software to clear the request queue
The request queues of the relevant channel are cleared by writing a 1 to the
CHCRn.QCL bit (request-queue clear bit) of each channel.
Note: *
DTR.COUNT [7:4] (DTR [23:20]): Sets the port as not used. In DDT mode on
the SH7751, an external device and the DMAC perform handshaking using the
DBREQ, BAVL, TR, TDACK, ID[1:0], and D[31:0] signals during data
transfer. On the SH7751R, the DBREQ, BAVL, TR, TDACK, ID[2:0], and
D[31:0] signals are used for handshaking during data transfer between an
external device and the DMAC.
Rev.4.00 Oct. 10, 2008 Page 499 of 1122
REJ09B0370-0400