HD6417751RBP240V Datasheet, PDF (525/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

13. Bus State Controller (BSC)
CKIO
TRr1 TRr2 TRr3 TRr4 TRr5 Trc Trc Trc
A25–A0
CSn
RD/WR
RAS
CAS
D31–D0
BS
Figure 13.21 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1)
• Self-Refresh
The self-refreshing supported by this LSI is shown in figure 13.22.
After the self-refresh is cleared, the refresh controller immediately generates a refresh request.
The RAS precharge time immediately after the end of the self-refreshing can be set by bits
TRC2–TRC0 in MCR.
CAS-before-RAS refreshing is performed in normal operation, in sleep mode, and in the case
of a manual reset.
Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the
case of a manual reset.
When the bus has been released in response to a bus arbitration request, or when a transition is
made to standby mode, signals generally become high-impedance, but whether the RAS and
CAS signals become high-impedance or continue to be output can be controlled by the
HIZCNT bit in BCR1. This enables the DRAM to be kept in the self-refreshing state.
Rev.4.00 Oct. 10, 2008 Page 425 of 1122
REJ09B0370-0400