HD6417751RBP240V Datasheet, PDF (658/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. Direct Memory Access Controller (DMAC)
14.5.3 Transfer Request Acceptance on Each Channel
On channel 0, a DMA data transfer request can be made by means of the DTR format. No further
transfer requests are accepted between DTR format acceptance and the end of the data transfer.
On channels 1 to 3, output a transfer request from an external device by means of the DTR format
(ID = 01, 10, or 11) after making DMAC control register settings in the same way as in normal
DMA mode. Each of channels 1 to 3 has a request queue that can accept up to four transfer
requests. When a request queue is full, the fifth and subsequent transfer requests will be ignored,
and so transfer requests must not be output. When CHCR.TE = 1 when a transfer request remains
in the request queue and a transfer is completed, the request queue retains it. When another
transfer request is sent at that time, the transfer request is added to the request queue if the request
queue is vacant.
Rev.4.00 Oct. 10, 2008 Page 558 of 1122
REJ09B0370-0400