HD6417751RBP240V Datasheet, PDF (929/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

21. High-performance User Debug Interface (H-UDI)
21.2.4 Interrupt Factor Register (SDINT)
The interrupt factor register (SDINT) is a 16-bit register that can be read/written from the CPU.
When a (H-UDI interrupt) command is set in the SDIR (Update-IR) via the H-UDI pin, the
INTREQ bit is set to 1. While SDIR has the “H-UDI interrupt” command, the SDINT register is
connected between H-UDI pins TDI and TDO, and can be read as a 32-bit register. The high 16
bits are 0 and the low 16 bits are SDINT.
Only 0 can be written to the INTREQ bit from the CPU. While this bit is 1, the interrupt request
continues to be generated, and must therefore be cleared to 0 by the interrupt handler. This register
is initialized by TRST or when in the Test Logic Reset state.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
— INTREQ
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bits 15 to 1— Reserved: These bits always read as 0, and should only be written with 0.
Bit 0—Interrupt Request Bit (INTREQ): Shows the existence of an interrupt request from the
“H-UDI interrupt” command. The interrupt request can be cleared by writing 0 to this bit from the
CPU. When 1 is written to this bit, the existing value is retained.
21.2.5 Boundary Scan Register (SDBSR)
The boundary scan register (SDBSR) is a shift register that is placed on the pads to control the
chip's I/O pins. This register can perform a boundary scan test equivalent to the JTAG (IEEE Std
1149.1) standard using EXTEST, SAMPLE, and PRELOAD commands. Table 21.3 shows the
relationship between this LSI pins and the boundary scan register.
Rev.4.00 Oct. 10, 2008 Page 829 of 1122
REJ09B0370-0400