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HD6417751RBP240V Datasheet, PDF (1161/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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23. Electrical Characteristics
23.3.4 Peripheral Module Signal Timing
Table 23.23 Peripheral Module Signal Timing (1)
HD6417751
RBP240 (V)
HD6417751
RBG240 (V)
*2
HD6417751
RBP200 (V)
HD6417751
RBG200 (V)
*2
HD6417751
RF240 (V)
*2
HD6417751
RF200 (V)
*2
Module Item
Symbol Min Max Min Max Min Max Min Max Unit Figure Notes
TMU, Timer clock tTCLKWH 4
â
RTC pulse width
(high)
4â
4â
4 â Pcyc*1 23.59
Timer clock tTCLKWL 4
â
pulse width
(low)
4â
4â
4 â Pcyc*1 23.59
Timer clock tTCLKr
rise time
â 0.8
â 0.8
â 0.8
â 0.8 Pcyc*1 23.59
Timer clock tTCLKf
fall time
â 0.8
â 0.8
â 0.8
â 0.8 Pcyc*1 23.59
Oscillation tROSC
settling time
â3
â3
â3
â3 s
23.60
SCI
Input clock tScyc
4â
4â
4â
4 â Pcyc*1 23.61
cycle (asyn-
chronous)
Input clock tScyc
cycle (syn-
chronous)
6â
6â
6â
6 â Pcyc*1 23.61
Input clock tSCKW
pulse width
0.4 0.6
0.4 0.6
0.4 0.6
0.4 0.6 tScyc 23.61
Input clock tSCKr
rise time
â 0.8 â 0.8 â 0.8 â 0.8 Pcyc*1 23.61
Input clock falltSCKf
time
â 0.8 â 0.8 â 0.8 â 0.8 Pcyc*1 23.61
Transfer data tTXD
delay time
1.5 5.3 1.5 5.3 1.5 6
1.5 6 ns 23.62
Receive data tRXS
setup time
(synchronous)
16 â
16 â
16 â 16 â ns 23.62
Receive data tRXH
hold time
(synchronous)
16 â
16 â
16 â
16 â ns 23.62
I/O
ports
Output data tPORTD
delay time
1.5 5.3
1.5 5.3
1.5 6
1.5 6 ns 23.63
Input data tPORTS 2
â
setup time
2.5 â
3.5 â
3.5 â ns 23.63
Input data
hold time
tPORTH
1.5 â
1.5 â
1.5 â
1.5 â ns 23.63
Rev.4.00 Oct. 10, 2008 Page 1061 of 1122
REJ09B0370-0400
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