HD6417751RBP240V Datasheet, PDF (219/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

4. Caches
• Data array
The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized
by a power-on or manual reset.
• LRU (SH7751R only)
In a 2-way set-associative system, up to two entry addresses can register the same data in
cache. The LRU bit indicates to which way the entry is to be registered among the two ways.
There is one LRU bit in each entry, and it is controlled by hardware. The LRU (Last Recently
Used) algorithm that selects the most recently accessed way is used for way selection. The
LRU bit is initialized to 0 by a power-on reset, but is not initialized by a manual reset. The
LRU bit cannot be read from or written to by software.
4.4.2 Read Operation
When the IC is enabled (CCR.ICE = 1) and instruction fetches are performed by means of an
effective address from a cacheable area, the instruction cache operates as follows:
1. The tag and V bit are read from the cache line indexed by effective address bits [12:5].
2. The tag is compared with bits [28:10] of the address resulting from effective address
translation by the MMU:
• If the tag matches and the V bit is 1
→ (3a)
• If the tag matches and the V bit is 0
→ (3b)
• If the tag does not match and the V bit is 0 → (3b)
• If the tag does not match and the V bit is 1 → (3b)
3a. Cache hit
The data indexed by effective address bits [4:2] is read as an instruction from the data field of
the cache line indexed by effective address bits [12:5].
3b. Cache miss
Data is read into the cache line from the external memory space corresponding to the effective
address. Data reading is performed, using the wraparound method, in order from the longword
data corresponding to the effective address, and when the corresponding data arrives in the
cache, the read data is returned to the CPU as an instruction. When reading of one line of data
is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is
written to the V bit.
Rev.4.00 Oct. 10, 2008 Page 119 of 1122
REJ09B0370-0400