HD6417751RBP240V Datasheet, PDF (222/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

4. Caches
4.5.2 IC Data Array
The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The entry to be accessed is specified in the address field, and the longword
data to be written is specified in the data field.
In the address field, bits [31:24] have the value H'F1 indicating the IC data array, and the entry is
specified by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2]
are used for the longword data specification in the entry. As only longword access is used, 0
should be specified for address field bits [1:0].
The data field is used for the longword data specification.
The following two kinds of operation can be used on the IC data array:
1. IC data array read
Longword data is read into the data field from the data specified by the longword specification
bits in the address field in the IC entry corresponding to the entry set in the address field.
2. IC data array write
The longword data specified in the data field is written for the data specified by the longword
specification bits in the address field in the IC entry corresponding to the entry set in the
address field.
31
24 23
Address field _{1 1 1 1 0 0 0 1}
13 12
Entry
54 210
L
31
0
Data field
Longword data
Legend:
L: Longword specification bits
: Reserved bits (0 write value, undefined read value)
Figure 4.9 Memory-Mapped IC Data Array
Rev.4.00 Oct. 10, 2008 Page 122 of 1122
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