HD6417751RBP240V Datasheet, PDF (527/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

13. Bus State Controller (BSC)
Power-On Sequence: Regarding use of DRAM after powering on, it is requested that a wait time
(at least 100 μs or 200 μs) during which no access can be performed be provided, followed by at
least the prescribed number (usually 8) of dummy CAS-before-RAS refresh cycles. As the bus
state controller does not perform any special operations for a power-on reset, the necessary power-
on sequence must be carried out by the initialization program executed after a power-on reset.
13.3.5 Synchronous DRAM Interface
Direct Connection of Synchronous DRAM: Since synchronous DRAM can be selected by the
CS signal, it can be connected to external memory space areas 2 and 3 using RAS and other
control signals in common. If the memory type bits (DRAMTP2–0) in BCR1 are set to 010, area 3
is synchronous DRAM interface; if set to 011, areas 2 and 3 are both synchronous DRAM
interface.
This LSI supports burst read and burst write operations with a burst length of 4 as a synchronous
DRAM operating mode. The data bus width is 32 bit, and the SZ size bits in MCR must be set to
11. The burst enable bit (BE) in MCR is ignored, a 32-byte burst transfer is performed in a cache
fill/copy-back cycle. In write-through area write operations and non-cacheable area read/write
operations, 16-byte data is read even in a single read because accessing synchronous DRAM is by
burst-length 4 burst read/write operations. 16-byte data transfer is also performed in a single write,
but DQMn is not asserted when unnecessary data is transferred.
In the SH7751R, an 8-burst-length burst read/burst write mode is also supported as a synchronous
DRAM operating mode. The data bus width is 32 bits, and the SZ size bits in MCR must be set to
11. Burst enable bit BE in MCR is ignored, and a 32-byte burst transfer is performed in a cache
fill/copy-back cycle. For write-through area writes and non-cacheable area reads/writes,
synchronous DRAM is accessed with an 8-burst-length burst read/write, and therefore 32 bytes of
data are read even in the case of a single read. In the case of a single write, 32-byte data transfer is
performed but DQMn is not asserted in the case of an unnecessary data transfer. For a description
of the case where an 8-burst-length setting is made, see section 13.3.6, Burst ROM Interface. For
information on the burst length, see section 13.2.10, Synchronous DRAM Mode Register
(SDMR), and section 13.3.5, Power-On Sequence.
The control signals for connection of synchronous DRAM are RAS, CASS, RD/WR, CS2 or CS3,
DQM0 to DQM3, and CKE. All the signals other than CS2 and CS3 are common to all areas, and
signals other than CKE are valid and latched only when CS2 or CS3 is asserted. Synchronous
DRAM can therefore be connected in parallel to a number of areas. CKE is negated (driven low)
when the frequency is changed, when the clock is unstable after the clock supply is stopped and
restarted, or when self-refreshing is performed, and is always asserted (high) at other times.
Rev.4.00 Oct. 10, 2008 Page 427 of 1122
REJ09B0370-0400