HD6417751RBP240V Datasheet, PDF (604/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. Direct Memory Access Controller (DMAC)
14.2 Register Descriptions
14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)
Bit: 31
30
29
28
27
26
25
24
Initial value: —
—
—
—
—
—
—
—
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 23
0
·············································
Initial value: —
·············································
—
R/W: R/W
·············································
R/W
DMA source address registers 0–3 (SAR0–SAR3) are 32-bit readable/writable registers that
specify the source address of a DMA transfer. These registers have a counter feedback function,
and during a DMA transfer they indicate the next source address. In single address mode, the SAR
value is ignored when a device with DACK has been specified as the transfer source.
Specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64-
bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will
be detected and the DMAC will halt.
The initial value of these registers after a power-on or manual reset is undefined. They retain their
values in standby mode, sleep mode, and deep sleep mode.
Rev.4.00 Oct. 10, 2008 Page 504 of 1122
REJ09B0370-0400