HD6417751RBP240V Datasheet, PDF (1032/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

22. PCI Controller (PCIC)
Inter-PCI Device Arbitration: The PCI bus arbitration circuit in the PCIC can be used when the
PCIC is operating as the host device. The arbitration circuit can be connected to up to four external
PCI devices (devices that can operate as master devices) that request bus privileges.
If multiple bus privilege requests are made simultaneously by the PCI devices, the bus privilege is
grated in the predetermined order of priority. There are two orders of priority: fixed, and pseudo
round robin. The mode is selected by setting the bus master arbitration mode control bit (BMABT)
of the PCI control register (PCICR).
• Priority-fixed mode (BMABT = 0)
In priority-fixed mode, the priority order of bus privilege requests is fixed and cannot be
changed. The order is as follows:
PCIC (device 0) > device 1 > device 2 > device 3 > device 4
That is, the PCIC has the highest order of priority and device 4 has the lowest. When bus
privilege requests occur simultaneously, the device with the highest order of priority takes
precedence. Here, device 1 is the PCI device using bus privilege request pins PCIREQ1 and
PCIGNT1, device 2 uses PCIREQ2 and PCIGNT2, device 3 uses PCIREQ3 and PCIGNT3,
and device 4 uses PCIREQ4 and PCIGNT4. When the PCIC is operating as the host device, no
bus privilege request signals are output from the PCIC to the PCI bus arbitration circuit.
• Pseudo round-robin mode (BMABT = 1)
In pseudo round-robin mode, when a device takes the bus privilege, the priority order of that
device becomes lowest.
In the initial state, the priority order is set to the same as in the fixed mode. Here, device 1
outputs a bus privilege request, after which the priority order changes to …
PCIC > device 2 > device 3 > device 4 > device 1.
If the PCIC then outputs a bus privilege request and takes the bus privilege, the priority order
changes to …
Device 2 > device 3 > device 4 > device 1 > PCIC.
Likewise, if device 3 outputs a bus privilege request and takes the bus privilege, the priority
order becomes …
Device 2 > device 4 > device 1 > PCIC > device 3.
In this way, the priority order of the master device that takes the bus privilege always changes
to lowest after the data transfer is completed.
Rev.4.00 Oct. 10, 2008 Page 932 of 1122
REJ09B0370-0400