HD6417751RBP240V Datasheet, PDF (528/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

13. Bus State Controller (BSC)
Commands for synchronous DRAM are specified by RAS, CASS, RD/WR, and specific address
signals. The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks
(PALL), precharge specified bank (PRE), row address strobe bank active (ACTV), read (READ),
read with precharge (READA), write (WRIT), write with precharge (WRITA), and mode register
setting (MRS).
Byte specification is performed by DQM0 to DQM3. A read/write is performed for the byte for
which the corresponding DQM signal is low. When the bus width is 32 bits, in big-endian mode
DQM3 specifies an access to address 4n, and DQM0 specifies an access to address 4n + 3. In
little-endian mode, DQM3 specifies an access to address 4n + 3, and DQM0 specifies an access to
address 4n.
Figure 13.23 shows examples of the connection of 16M × 16-bit synchronous DRAMs.
SH7751/SH7751R
A11–A2
CKIO
CKE
CS3
RAS
CASS
RD/WR
D31–D16
DQM3
DQM2
512k × 16-bit × 2-bank
synchronous DRAM
A9–A0
CLK
CKE
CS
RAS
CAS
WE
I/O15–I/O0
DQMU
DQML
D15–D0
DQM1
DQM0
A9–A0
CLK
CKE
CS
RAS
CAS
WE
I/O15–I/O0
DQMU
DQML
Figure 13.23 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3)
Rev.4.00 Oct. 10, 2008 Page 428 of 1122
REJ09B0370-0400