HD6417751RBP240V Datasheet, PDF (303/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

7. Instruction Set
Table 7.8 System Control Instructions
Instruction
CLRMAC
CLRS
CLRT
LDC
Rm,SR
LDC
Rm,GBR
LDC
Rm,VBR
LDC
Rm,SSR
LDC
Rm,SPC
LDC
Rm,DBR
LDC
Rm,Rn_BANK
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDC.L @Rm+,SSR
LDC.L @Rm+,SPC
LDC.L @Rm+,DBR
LDC.L @Rm+,Rn_BANK
LDS
Rm,MACH
LDS
Rm,MACL
LDS
Rm,PR
LDS.L @Rm+,MACH
LDS.L @Rm+,MACL
LDS.L @Rm+,PR
LDTLB
MOVCA.L R0,@Rn
NOP
OCBI
OCBP
@Rn
@Rn
OCBWB @Rn
PREF @Rn
RTE
Operation
Instruction Code
Privileged
0 → MACH, MACL
0000000000101000 —
0→S
0000000001001000 —
0→T
0000000000001000 —
Rm → SR
0100mmmm00001110 Privileged
Rm → GBR
0100mmmm00011110 —
Rm → VBR
0100mmmm00101110 Privileged
Rm → SSR
0100mmmm00111110 Privileged
Rm → SPC
0100mmmm01001110 Privileged
Rm → DBR
0100mmmm11111010 Privileged
Rm → Rn_BANK (n = 0 to 7) 0100mmmm1nnn1110 Privileged
(Rm) → SR, Rm + 4 → Rm
0100mmmm00000111 Privileged
(Rm) → GBR, Rm + 4 → Rm 0100mmmm00010111 —
(Rm) → VBR, Rm + 4 → Rm 0100mmmm00100111 Privileged
(Rm) → SSR, Rm + 4 → Rm 0100mmmm00110111 Privileged
(Rm) → SPC, Rm + 4 → Rm 0100mmmm01000111 Privileged
(Rm) → DBR, Rm + 4 → Rm 0100mmmm11110110 Privileged
(Rm) → Rn_BANK,
Rm + 4 → Rm
0100mmmm1nnn0111 Privileged
Rm → MACH
0100mmmm00001010 —
Rm → MACL
0100mmmm00011010 —
Rm → PR
0100mmmm00101010 —
(Rm) → MACH, Rm + 4 → Rm 0100mmmm00000110 —
(Rm) → MACL, Rm + 4 → Rm 0100mmmm00010110 —
(Rm) → PR, Rm + 4 → Rm
0100mmmm00100110 —
PTEH/PTEL → TLB
0000000000111000 Privileged
R0 → (Rn) (without fetching
cache block)
0000nnnn11000011 —
No operation
0000000000001001 —
Invalidates operand cache block 0000nnnn10010011 —
Writes back and invalidates
operand cache block
0000nnnn10100011 —
Writes back operand cache block0000nnnn10110011 —
(Rn) → operand cache
0000nnnn10000011 —
Delayed branch, SSR/SPC → 0000000000101011 Privileged
SR/PC
T Bit
—
—
0
LSB
—
—
—
—
—
—
LSB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Rev.4.00 Oct. 10, 2008 Page 203 of 1122
REJ09B0370-0400