HD6417751RBP240V Datasheet, PDF (909/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

20. User Break Controller (UBC)
• Example of sequence of instructions with a branch (however, the example of a sequence of
instructions with no branch should be applied when the branch destination of a delayed branch
instruction is the instruction itself + 4):
100 Instruction A: BT/S L200 (0 instructions after instruction A)
102 Instruction B (1 instruction after instruction A, 0 instructions after instruction B)
L200 200 Instruction C (3 instructions after instruction A, 2 instructions after instruction B)
202 Instruction D (4 instructions after instruction A, 3 instructions after instruction B)
20.3.3 User Break Operation Sequence
The sequence of operations from setting of break conditions to user break exception handling is
described below.
1. Specify pre- or post-execution breaking in the case of an instruction access, inclusion or
exclusion of the data bus value in the break conditions in the case of an operand access, and
use of independent or sequential channel A and B break conditions, in the break control
register (BRCR). Set the break addresses in the break address registers for each channel
(BARA, BARB), the ASIDs corresponding to the break space in the break ASID registers
(BASRA, BASRB), and the address and ASID masking methods in the break address mask
registers (BAMRA, BAMRB). If the data bus value is to be included in the break conditions,
also set the break data in the break data register (BDRB) and the data mask in the break data
mask register (BDMRB).
2. Set the break bus conditions in the break bus cycle registers (BBRA, BBRB). If even one of
the BBRA/BBRB instruction access/operand access select (ID bit) and read/write select groups
(RW bit) is set to 00, a user break interrupt will not be generated on the corresponding channel.
Make the BBRA and BBRB settings after all other break-related register settings have been
completed. If breaks are enabled with BBRA/BBRB while the break address, data, or mask
register, or the break control register is in the initial state after a reset, a break may be
generated inadvertently.
3. The operation when a break condition is satisfied depends on the BL bit (in the CPU's SR
register). When the BL bit is 0, exception handling is started and the condition match flag
(CMFA/CMFB) for the respective channel is set for the matched condition. When the BL bit is
1, the condition match flag (CMFA/CMFB) for the respective channel is set for the matched
condition but exception handling is not started.
The condition match flags (CMFA, CMFB) are set by a branch condition match, but are not
reset. Therefore, a memory store instruction should be used on the BRCR register to clear the
flags to 0. See section 20.3.6, Condition Match Flag Setting, for the exact setting conditions for
the condition match flags.
Rev.4.00 Oct. 10, 2008 Page 809 of 1122
REJ09B0370-0400