HD6417751RBP240V Datasheet, PDF (554/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

13. Bus State Controller (BSC)
command, to be completed in the synchronous DRAM. During this cycle, no new command
that accesses the same bank can be issued. In this LSI, the number of Tpc cycles is determined
by the setting of the TPC2 to TPC0 bits of the MCR, and no command that operates on the
synchronous DRAM is issued during these cycles.
Figure 13.39 shows an example of the basic timing of a burst-read. To allow the connection of
a lower-speed DRAM, the cycle's period can be extended by the settings of the bits in WCR2
and MCR. The number of cycles from cycle Tr on which the ACTV command is output to
cycle Tc1 on which the READA command is output can be specified by the RCD1 and RCD0
bits in MCR: the number of cycles is 2, 3, or 4 for the setting value of 1, 2, or 3, respectively.
When two or more cycles are specified, the Trw cycle, which is for the issuing of NOP
commands to the synchronous DRAM, is inserted between the Tr and Tc cycles. The number
of cycles from cycle Tc1 on which the READA command is output until cycle Td1, in which
the first part of the data to be read is received, can be set by the bits A2W2 to A2W0 and
A3W2 to A3W0 of WCR2. These independently select a number of cycles between 1 and 5 for
areas 2 and 3. Note that this number of cycles is equal to the number of CAS latency cycles of
the synchronous DRAM.
Rev.4.00 Oct. 10, 2008 Page 454 of 1122
REJ09B0370-0400