HD6417751RBP240V Datasheet, PDF (513/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

13. Bus State Controller (BSC)
13.3.4 DRAM Interface
Direct Connection of DRAM: When the memory type bits (DRAMTP2–0) in BCR1 are set to
100, area 3 becomes DRAM interface. The DRAM interface function can then be used to connect
DRAM to this LSI.
16 or 32 bits can be selected as the interface data width.
2-CAS 16-bit DRAMs can be connected, since CAS is used to control byte access.
Signals used for connection are CS3, RAS, CAS0 to CAS3, and RD/WR. CAS2 to CAS3 are not
used when the data width is 16 bits.
In addition to normal read and write access modes, fast page mode is supported for burst access.
EDO mode, which enables the DRAM access time to be increased, is supported.
SH7751/SH7751R
A10
A2
256K × 16-bit
DRAM
A8
A0
RAS
CS3
RD/WR
D31
D16
CAS3
CAS2
D15
D0
CAS1
CAS0
RAS
OE
WE
I/O15
I/O0
UCAS
LCAS
A8
A0
RAS
OE
WE
I/O15
I/O0
UCAS
LCAS
Figure 13.13 Example of DRAM Connection (32-Bit Data Width, Area 3)
Rev.4.00 Oct. 10, 2008 Page 413 of 1122
REJ09B0370-0400