 English |
|
|
|
|
|
|
|
| HD6417751RBP240V Datasheet, PDF (689/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
| |||
| ◁ |
14. Direct Memory Access Controller (DMAC)
14.7.3 DMA Transfer Count Registers 0â7 (DMATCR0âDMATCR7)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0 0 â â â â â â â â
R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: â â â â â â â â â â â â â â â â
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DMA transfer count registers 0â7 (DMATCR0âDMATCR7) are 32-bit readable/writable registers
that specify the number of transfers in transfer operations for the corresponding channel
(bytecount, word count, longword count, quadword count, or 32-byte count). Functions of these
registers are the same as the transfer-count registers of the SH7751. For more information, see
section 14.2.3, DMA Transfer Count Registers 0â3 (DMATCR0âDMATCR3).
14.7.4 DMA Channel Control Registers 0â7 (CHCR0âCHCR7)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SSA2 SSA1 SSA0 STC DSA2 DSA1 DSA0 DTC â â â â DS RL AM AL
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W (R/W) R/W (R/W)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 TM TS2 TS1 TS0 QCL IE TE DE
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (R/W) R/W (R/W) R/W
DMA channel control registers 0â7 (CHCR0âCHCR7) are 32-bit readable/writable registers that
specify the operating mode, transfer method, etc., for each channel. Bits 31â28 and 27â24
correspond to the source address and destination address, respectively; these settings are only valid
when the transfer involves the CS5 or CS6 space and the relevant space has been specified as a
PCMCIA-interface space. In other cases, these bits should be cleared to 0. For more information
about the PCMCIA interface, see section 13.3.7, PCMCIA Interface.
Rev.4.00 Oct. 10, 2008 Page 589 of 1122
REJ09B0370-0400
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese