HD6417751RBP240V Datasheet, PDF (790/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

16. Serial Communication Interface with FIFO (SCIF)
SCFCR2 performs data count resetting and trigger data number setting for the transmit and receive
FIFO registers, and also contains a loopback test enable bit.
SCFCR2 can be read or written to by the CPU at all times.
SCFCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Bits 15 to 11—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 10, 9 and 8—RTS2 Output Active Trigger (RSTRG2, RSTG1, and RSTG0): These bits
output the high level to the RTS2 signal when the number of received data stored in the receive
FIFO data register (SCFRDR2) exceeds the trigger number, as shown in the table below.
Bit 10: RSTRG2 Bit 9: RSTRG1
0
0
1
1
0
1
Bit 8: RSTRG0
0
1
0
1
0
1
0
1
RTS2 Output Active Trigger
15
(Initial value)
1
4
6
8
10
12
14
Bits 7 and 6—Receive FIFO Data Number Trigger (RTRG1, RTRG0): These bits are used to
set the number of receive data bytes that sets the receive data full (RDF) flag in the serial status
register (SCFSR2).
The RDF flag is set when the number of receive data bytes in SCFRDR2 is equal to or greater than
the trigger set number shown in the following table.
Bit 7: RTRG1
0
1
Bit 6: RTRG0
0
1
0
1
Receive Trigger Number
1
4
8
14
(Initial value)
Rev.4.00 Oct. 10, 2008 Page 690 of 1122
REJ09B0370-0400