HD6417751RBP240V Datasheet, PDF (23/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Item
12.2.7 Input Capture
Register 2 (TCPR2)
12.4 Interrupts
Page
326
332
12.5.4 External Clock 333
Frequency
13.1.4 Register
340
Configuration
Table 13.2 BSC
Registers
13.1.6 PCMCIA
347
Support
Table 13.5 PCMCIA
Support Interfaces
13.2.3 Bus Control 359
Register 3 (BCR3)
(SH7751R Only)
13.2.7 Wait Control 375
Register 3 (WCR3)
Revision (See Manual for Details)
Title amended
Description amended
There are six TMU interrupt sources, comprising underflow
interrupts and the input capture interrupt (when the input
capture function is used). Underflow interrupts are generated
on channels 0 to 4, and input capture interrupts on channel 2
only.
Description amended
Ensure that the external clock frequency for any channel does
not exceed Pck/8.
Table amended
Name
Bus control register 3*²
Abbrevia- R/W
tion
BCR3
R/W
Initial
Value
H'0001
Table and notes amended
Corresponding
Pin LSI Pin
57 —
58 Output from port
59 RDY*²
Notes: 1. WP is not supported.
2. Input an external wait request with correct polarity.
Description amended
BCR3 is initialized to H'0001 by a power-on reset, but is not
initialized by a manual reset or in standby mode.
Description amended of Bits 4n+3
Bits 4n+3⎯Area n (4 or 1) Read-Strobe Negate Timing
(AnRDH) (Setting Only Possible in the SH7751R): When
reading, these bits specify the timing for the negation of read
strobe. These bits should be cleared to 0 when a byte control
SRAM setting is made.
Valid only for the SRAM
interface.
Bit 4n + 3: AnRDH
0
1
Read-Strobe Negate Timing
Read strobe negated after hold wait cycles specified by WCR3.AnH bits
(Initial value)
Read strobe negated according to data sampling timing
Note: n = 4 or 1
Rev.4.00 Oct. 10, 2008 Page xxi of xcviii
REJ09B0370-0400