HD6417751RBP240V Datasheet, PDF (449/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

13. Bus State Controller (BSC)
Bit 31—Endian Flag (ENDIAN): Samples the value of the endian specification external pin
(MD5) in a power-on reset by means of the RESET pin. The endian mode of all spaces is
determined by this bit. ENDIAN is a read-only bit.
Bit 31: ENDIAN
0
1
Description
In a power-on reset, the endian setting external pin (MD5) is low,
designating big-endian mode for this LSI
In a power-on reset, the endian setting external pin (MD5) is high,
designating little-endian mode for this LSI
Bit 30—Master/Slave Flag (MASTER): Samples the value of the master/slave specification
external pin (MD7) in a power-on reset by means of the RESET pin. The master/slave status of all
spaces is determined by this bit. MASTER is a read-only bit.
Bit 30: MASTER
0
1
Description
In a power-on reset, the master/slave setting external pin (MD7) is high,
designating master mode for this LSI
In a power-on reset, the master/slave setting external pin (MD7) is low,
designating slave mode for this LSI
Bit 29—Area 0 Memory Type (A0MPX): Samples the value of the area 0 memory type
specification external pin (MD6) in a power-on reset by means of the RESET pin. The memory
type of area 0 is determined by this bit. A0MPX is a read-only bit.
Bit 29: A0MPX
0
1
Description
In a power-on reset, the external pin specifying the area 0 memory type
(MD6) is high, designating the area 0 as SRAM interface
In a power-on reset, the external pin specifying the area 0 memory type
(MD6) is low, designating the area 0 as MPX interface
Bits 28, 27, 23, 22, 18, and 1—Reserved: These bits are always read as 0, and the write value
should always be 0.
Rev.4.00 Oct. 10, 2008 Page 349 of 1122
REJ09B0370-0400