HD6417751RBP240V Datasheet, PDF (425/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12. Timer Unit (TMU)
The TCNT2 value is set in TCPR2 only when the TCR2.ICPF bit is 0. When the TCR2.ICPF bit is
1, TCPR2 is not set in the event of input capture. When input capture occurs, a DMAC transfer
request is generated regardless of the value of the TCR2.ICPF bit. However, a new DMAC
transfer request is not generated until processing of the previous request is finished.
Bit 7: ICPE1
0
1
Bit 6: ICPE0
0
1
0
1
Description
Input capture function is not used
(Initial value)
Reserved (Do not set)
Input capture function is used, but interrupt due to input capture
(TICPI2) is not enabled
Data transfer request is sent to DMAC in the event of input
capture
Input capture function is used, and interrupt due to input
capture (TICPI2) is enabled
Data transfer request is sent to DMAC in the event of input
capture
Bit 5—Underflow Interrupt Control (UNIE): Controls enabling or disabling of interrupt
generation when the UNF status flag is set to 1, indicating TCNT underflow.
Bit 5: UNIE
0
1
Description
Interrupt due to underflow (TUNI) is not enabled
Interrupt due to underflow (TUNI) is enabled
(Initial value)
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): In channels 0 to 2, these bits select the
external clock input edge when an external clock is selected or the input capture function is used.
Bit 4: CKEG1 Bit 3: CKEG0
0
0
1
1
X
Note: X: 0 or 1 (don't care)
Description
Count/input capture register set on rising edge (Initial value)
Count/input capture register set on falling edge
Count/input capture register set on both rising and falling edges
Rev.4.00 Oct. 10, 2008 Page 325 of 1122
REJ09B0370-0400