HD6417751RBP240V Datasheet, PDF (959/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

22. PCI Controller (PCIC)
Bit 28—Target Abort Receive Status (RTA): Indicates the termination of transaction by master
abort when the PCIC is operating as the master.
Bit 28: RTA
0
1
Description
No transaction termination using target abort
(Initial value)
Detection by bus master of transaction termination by target abort
Bit 27—Target Abort Execution Status (STA): Indicates the termination of transaction by target
abort when the PCIC is operating as the target.
Bit 27: STA
0
1
Description
No transaction termination using target abort by target device (Initial value)
Transaction termination by target abort by target device. Notification by
target device
Bits 26 and 25—DEVSEL Timing Status (DEV1 and 0): These bits indicate the DEVSEL
response timing when the PCIC is operating as a target.
Bit 26: DEV1
0
1
Bit 25: DEV0
0
1
0
1
Description
High-speed (not supported)
Medium speed
Low speed (not supported)
Reserved
(Initial value)
Bit 24—Data Parity Status (DPD): Indicates the PERR assert operation or the detection of
PERR when the PCIC is operating as the master. This bit is set only when the parity error response
bit (bit 6) is 1.
Bit 24: DPD
0
1
Description
Data parity not detected
Data parity occurred
(Initial value)
Rev.4.00 Oct. 10, 2008 Page 859 of 1122
REJ09B0370-0400