HD6417751RBP240V Datasheet, PDF (86/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Figure 17.13 Procedure for Stopping and Restarting the Clock .................................................. 744
Section 18 I/O Ports
Figure 18.1 16-Bit Port A .......................................................................................................... 748
Figure 18.2 16-Bit Port B .......................................................................................................... 749
Figure 18.3 SCK Pin.................................................................................................................. 750
Figure 18.4 TxD Pin .................................................................................................................. 751
Figure 18.5 RxD Pin.................................................................................................................. 751
Figure 18.6 MD1/TxD2 Pin....................................................................................................... 752
Figure 18.7 MD2/RxD2 Pin ...................................................................................................... 752
Figure 18.8 MD0/SCK2 Pin ...................................................................................................... 753
Figure 18.9 MD7/CTS2 Pin....................................................................................................... 754
Figure 18.10 MD8/RTS2 Pin....................................................................................................... 755
Section 19 Interrupt Controller (INTC)
Figure 19.1 Block Diagram of INTC......................................................................................... 770
Figure 19.2 Example of IRL Interrupt Connection.................................................................... 773
Figure 19.3 Interrupt Operation Flowchart................................................................................ 788
Section 20 User Break Controller (UBC)
Figure 20.1 Block Diagram of User Break Controller............................................................... 796
Figure 20.2 User Break Debug Support Function Flowchart .................................................... 817
Section 21 High-performance User Debug Interface (H-UDI)
Figure 21.1 Block Diagram of H-UDI Circuit........................................................................... 824
Figure 21.2 TAP Control State Transition Diagram.................................................................. 843
Figure 21.3 H-UDI Reset........................................................................................................... 844
Section 22 PCI Controller (PCIC)
Figure 22.1 PCIC Block Diagram ............................................................................................. 848
Figure 22.2 PIO Memory Space Access.................................................................................... 936
Figure 22.3 PIO I/O Space Access ............................................................................................ 937
Figure 22.4 Local Address Space Accessing Method ............................................................... 938
Figure 22.5 Example of DMA Transfer Control Register Settings ........................................... 942
Figure 22.6 Example of DMA Transfer Flowchart ................................................................... 944
Figure 22.7 Master Write Cycle in Host Mode (Single)............................................................ 948
Figure 22.8 Master Read Cycle in Host Mode (Single)............................................................. 949
Figure 22.9 Master Memory Write Cycle in Non-Host Mode (Burst) ...................................... 950
Figure 22.10 Master Memory Read Cycle in Non-Host Mode (Burst) ....................................... 951
Figure 22.11 Target Read Cycle in Non-Host Mode (Single) ..................................................... 953
Rev.4.00 Oct. 10, 2008 Page lxxxiv of xcviii
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