HD6417751RBP240V Datasheet, PDF (25/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Item
13.3.2 Areas
Area 0:
Area 1:
Page
400
Area 2:
401
Area 3:
Area 4:
402
Area 5:
403
Area 6:
404
13.3.3 SRAM Interface 412
Figure 13.12 SRAM
Interface Wait State
Timing (Read Strobe
Negate Timing Setting)
Revision (See Manual for Details)
Description amended
Area 0: For area 0, external address bits 28 to 26 are 000.
Description amended
Area 1: For area 1, external address bits 28 to 26 are 001.
Description amended
Area 2: For area 2, external address bits 28 to 26 are 010.
Description amended
Area 3: For area 3, external address bits 28 to 26 are 011.
Description amended
Area 4: For area 4, physical address bits 28 to 26 are 100.
Description amended
Area 5: For area 5, external address bits 28 to 26 are 101.
Description amended
Area 6: For area 6, external address bits 28 to 26 are 110.
Figure amended
TS1 T1 Tw Tw Tw Tw T2 TH1 TH2
CKIO
A25–A0
CSn
RD/WR
*
RD
D31–D0
BS
TS1: Setup wait
WCR3.AnS
(0 to 1)
Note: * When AnRDH is set to 1
Tw: Access wait
WCR2.AnW
(0 to 15)
TH1, TH2: Hold wait
WCR3.AnH
(0 to 3)
Rev.4.00 Oct. 10, 2008 Page xxiii of xcviii
REJ09B0370-0400