HD6417751RBP240V Datasheet, PDF (1015/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

22. PCI Controller (PCIC)
22.2.33 Memory Space Base Register (PCIMBR)
Bit:
Initial value:
PCI-R/W:
PP Bus-R/W:
31
MBR31
0
—
R/W
30
MBR30
0
—
R/W
29
MBR29
0
—
R/W
28
MBR28
0
—
R/W
27
MBR27
0
—
R/W
26
MBR26
0
—
R/W
25
MBR25
0
—
R/W
24
MBR24
0
—
R/W
Bit: 23
22
21
20
19
18
17
16
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
LOCK
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R
R
R
R
R
R
R
R/W
The memory space base register (PCIMBR) specifies the most significant 8 bits of the address of
the PCI memory space when performing a memory read/write operation using PIO transfers. It
also specifies locked transfers. This 32-bit read/write register can be accessed from the PP bus.
All bits of the PCIMBR register are initialized to 0 at a power-on reset. They are not initialized at
a software reset.
Setting bit 0 (LOCK) to 1 locks the memory space for PIO transfers while the bit remains set. A
locked transfer consists of the combined read and write operations. Do not attempt to perform
other PIO transfers during the locked combination of read and write operations.
Rev.4.00 Oct. 10, 2008 Page 915 of 1122
REJ09B0370-0400