HD6417751RBP240V Datasheet, PDF (246/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

5. Exceptions
5.5.3 Exception Requests and BL Bit
When the BL bit in SR is 0, general exceptions and interrupts are accepted.
When the BL bit in SR is 1 and a general exception other than a user break is generated, the CPU's
internal registers and the registers of the other modules are set to their post-reset state, and the
CPU branches to the same address as in a reset (H'A000 0000). For the operation in the event of a
user break, see section 20, User Break Controller (UBC).
If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the BL
bit has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can be held
pending or accepted according to the setting made by software.
Thus, normally, SPC and SSR are saved and then the BL bit in SR is cleared to 0, to enable
multiple exception state acceptance.
5.5.4 Return from Exception Handling
The RTE instruction is used to return from exception handling. When the RTE instruction is
executed, the SPC contents are restored to PC and the SSR contents to SR, and the CPU returns
from the exception handling routine by branching to the SPC address. If SPC and SSR were saved
to external memory, set the BL bit in SR to 1 before restoring the SPC and SSR contents and
issuing the RTE instruction.
5.6 Description of Exceptions
The various exception handling operations are described here, covering exception sources,
transition addresses, and processor operation when a transition is made.
Rev.4.00 Oct. 10, 2008 Page 146 of 1122
REJ09B0370-0400