HD6417751RBP240V Datasheet, PDF (613/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. Direct Memory Access Controller (DMAC)
Bit 7—Transmit Mode (TM): Specifies the bus mode for transfer.
Bit 7: TM
0
1
Description
Cycle steal mode
Burst mode
(Initial value)
Bits 6 to 4—Transmit Size 2 to 0 (TS2–TS0): These bits specify the transfer data size. In access
to external memory, the specification is treated as an access size as described in section 13.3,
Operation. In access to a register, the specification is treated as a register access size.
Bit 6: TS2
0
1
Bit 5: TS1
0
1
0
Bit 4: TS0
0
1
0
1
0
Description
Quadword size (64-bit) specification (Initial value)
Byte size (8-bit) specification
Word size (16-bit) specification
Longword size (32-bit) specification
32-byte block transfer specification
Bit 3—Reserved: This bit is always read as 0, and should only be written with 0.
Bit 2—Interrupt Enable (IE): When this bit is set to 1, an interrupt request (DMTE) is generated
after the number of data transfers specified in DMATCR (when TE = 1).
Bit 2: IE
0
1
Description
Interrupt request not generated after number of transfers specified in
DMATCR
(Initial value)
Interrupt request generated after number of transfers specified in DMATCR
Rev.4.00 Oct. 10, 2008 Page 513 of 1122
REJ09B0370-0400