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HD6417751RBP240V Datasheet, PDF (294/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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7. Instruction Set
Addressing
Mode
PC-relative
Instruction
Format
disp:12
Effective Address Calculation Method
Calculation
Formula
Effective address is PC+4 with 12-bit displacement PC + 4 + disp
disp added after being sign-extended and
à 2 â Branch-
multiplied by 2.
Target
PC
+
4
+
disp
(sign-extended)
Ã
PC + 4 + disp à 2
2
Rn
Effective address is sum of PC+4 and Rn.
PC + 4 + Rn
â Branch-
PC
Target
+
4
+
PC + 4 + Rn
Rn
Immediate #imm:8
8-bit immediate data imm of TST, AND, OR, or
â
XOR instruction is zero-extended.
#imm:8
8-bit immediate data imm of MOV, ADD, or
â
CMP/EQ instruction is sign-extended.
#imm:8
8-bit immediate data imm of TRAPA instruction is â
zero-extended and multiplied by 4.
Note:
For the addressing modes below that use a displacement (disp), the assembler descriptions
in this manual show the value before scaling (Ã1, Ã2, or Ã4) is performed according to the
operand size. This is done to clarify the operation of the chip. Refer to the relevant
assembler notation rules for the actual assembler descriptions.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, GBR) ; GBR indirect with displacement
@ (disp:8, PC) ; PC-relative with displacement
disp:8, disp:12 ; PC-relative
Rev.4.00 Oct. 10, 2008 Page 194 of 1122
REJ09B0370-0400
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