HD6417751RBP240V Datasheet, PDF (362/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9. Power-Down Modes
9.9.5 Hardware Standby Mode Timing
Figure 9.12 shows the timing of the signals of the respective pins in hardware standby mode.
The CA pin level must be kept low while in hardware standby mode.
After setting the RESET pin level low, the clock starts when the CA pin level is switched to high.
CKIO
CA
RESET
STATUS
Normal^*1
Standby^*2 Undefined Reset
0–10 Bcyc
Waiting for end of bus cycle
0–10 Bcyc
Notes: 1. Same at sleep and reset
2. High impedance when STBCR2. STHZ = 0
Figure 9.12 Hardware Standby Mode Timing
(When CA = Low in Normal Operation)
Rev.4.00 Oct. 10, 2008 Page 262 of 1122
REJ09B0370-0400