HD6417751RBP240V Datasheet, PDF (32/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Item
13.3.15 Notes on
Usage
Page Revision (See Manual for Details)
495, 496 Description amended
Refresh: Auto refresh operations stop when a transition is made
to standby mode, hardware standby mode, or deep-sleep
mode. If the memory system requires refresh operations, set
the memory in the self-refresh state prior to making the
transition to standby mode, hardware standby mode, or deep-
sleep mode.
…
Synchronous DRAM Mode Register Settings (SH7751 Only):
The following conditions must be satisfied when setting the
synchronous DRAM mode register.
• The DMAC must not be activated until synchronous DRAM
mode register setting is completed.*¹
• Register setting for the on-chip peripheral modules*² must
not be performed until synchronous DRAM mode register
setting is completed.*³
Notes: 1. If a conflict occurs between synchronous DRAM
mode register setting and memory access using the
DMAC, neither operation can be guaranteed.
2. This applies to the following on-chip peripheral
modules: CPG, RTC, INTC, TMU, SCI, SCIF, and
H-UDI.
3. If synchronous DRAM mode register setting is
performed immediately following write access to the
on-chip peripheral modules*², the values written to
the on-chip peripheral modules cannot be
guaranteed. Note that following power-on,
synchronous DRAM mode register settings should
be performed before accessing synchronous
DRAM. After making mode register settings, do not
change them.
Rev.4.00 Oct. 10, 2008 Page xxx of xcviii
REJ09B0370-0400