HD6417751RBP240V Datasheet, PDF (816/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

16. Serial Communication Interface with FIFO (SCIF)
16 clocks
8 clocks
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
Base clock
–7.5 clocks
+7.5 clocks
Receive data
(RxD2)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 16.14 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M=
(0.5 –
1 _{) – (L – 0.5) F –}
2N
| D – 0.5 |
N
(1 + F)
× 100%
......................
(1)
Legend:
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
M = (0.5 – 1 / (2 × 16) ) × 100% = 46.875% ............................................... (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Rev.4.00 Oct. 10, 2008 Page 716 of 1122
REJ09B0370-0400