HD6417751RBP240V Datasheet, PDF (534/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

13. Bus State Controller (BSC)
boundary data, and 32-byte boundary data is written in wraparound mode. DACK is asserted two
cycles before the data write cycle.
Figure 13.26 Basic Timing for Synchronous DRAM Burst Write
Rev.4.00 Oct. 10, 2008 Page 434 of 1122
REJ09B0370-0400