HD6417751RBP240V Datasheet, PDF (283/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Floating-Point Unit
⎯ Underflow (U):
When FPSCR.DN = 0, a denormalized number with the same sign as the unrounded value,
or zero with the same sign as the unrounded value, is generated.
When FPSCR.DN = 1, zero with the same sign as the unrounded value, is generated.
⎯ Inexact exception (I): An inexact result is generated.
6.6 Graphics Support Functions
The FPU supports two kinds of graphics functions: new instructions for geometric operations, and
pair single-precision transfer instructions that enable high-speed data transfer.
6.6.1 Geometric Operation Instructions
Geometric operation instructions perform approximate-value computations. To enable high-speed
computation with a minimum of hardware, the FPU ignores comparatively small values in the
partial computation results of four multiplications. Consequently, the error shown below is
produced in the result of the computation:
Maximum error = MAX (individual multiplication result ×
2 ) + MAX (result value × 2 , 2 ) ^{–MIN (number of multiplier significant digits–1, number of multiplicand significant digits–1)}
–23 –149
The number of significant digits is 24 for a normalized number and 23 for a denormalized number
(number of leading zeros in the fractional part).
In future version of SuperH RISC engine Family, the above error is guaranteed, but the same
result as SH7751 Group is not guaranteed.
FIPR FVm, FVn (m, n: 0, 4, 8, 12): Examples of the use of this instruction are given below.
• Inner product (m ≠ n):
This operation is generally used for surface/rear surface determination for polygon surfaces.
• Sum of square of elements (m = n):
This operation is generally used to find the length of a vector.
Since approximate-value computations are performed to enable high-speed computation, the
inexact exception (I) bit in the FPU exception cause field and FPU exception flag field is always
set to 1 when an FIPR instruction is executed. Therefore, if the corresponding bit is set in the FPU
exception enable field, FPU exception handling will be executed.
Rev.4.00 Oct. 10, 2008 Page 183 of 1122
REJ09B0370-0400