HD6417751RBP240V Datasheet, PDF (1039/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

22. PCI Controller (PCIC)
The PCICONF5 indicates the starting address of the memory space used by the PCI device. The
PCILAR0 specifies the starting address of the local address space 0. The PCILSR0 expresses the
size of the memory used by the PCI device. Regarding the method of setting each register, refer to
section 22.2, PCIC Register Descriptions.
For the PCICONF5 and PCILAR0, the most significant address bit that is higher than the memory
size set in the PCILSR0 becomes valid. The most significant address bit of the PCICONF5 and the
PCI address output from an external PCI device are compared for the purpose of determining
whether the access is made to the PCIC. When the addresses correspond, the access to the PCIC is
recognized, and a local address is generated from the most significant address bit of the PCILAR0
and the least significant bit of the PCI address output from the external PCI device. The PCI
command is executed for this local address.
If the most significant address bit of the PCI address output from the external PCI device does not
correspond with the most significant address bit of the PCICONF5, the PCIC does not respond to
the PCI command.
Address space 1 is, like address space 0, controlled by the PCICONF6, PCILSR1, and PCILAR1.
In this way, it is possible to set two address spaces. In systems with two or less local bus areas that
can be accessed from the PCI bus, separate address spaces can be allocated to each of them.
To make it possible to access two or more areas from the PCI bus, set the address spaces so that
multiple areas are covered. In this case, we can assume that the address space includes areas for
which no memory is installed. Note that, in this case, it is not possible to disable target transfers
to areas for which no memory is installed.
Note: See 22.3.11 (2), Target Read/Write Cycle Timing.
I/O-Read and I/O-Write Commands: The local registers of the PCIC are accessed by means of a
target transfer triggered by an I/O-read or I/O-write command. In the SH7751, accessing the local
registers by means of I/O transfer is made possible by setting a base address that specifies 1 Mbyte
of I/O space* in PCI configuration register 4 (PCICONF4). In the SH7751R, a base address that
specifies 256 bytes of I/O space should be set.
I/O-read and I/O-write commands only supports single transfers. The values of the byte-enable
signals (BE [3:0]) are ignored, and longword accesses are carried out inside the PCIC. When
executing an I/O-read and I/O-write commands transfer, specify B'0000 as the BE [3:0] value.
Note that some of the local registers are not accessible from the PCI bus. For details, see section
22.2, PCIC Register Descriptions.
Rev.4.00 Oct. 10, 2008 Page 939 of 1122
REJ09B0370-0400