HD6417751RBP240V Datasheet, PDF (1170/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

23. Electrical Characteristics
Table 23.26 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (2)
HD6417751BP167 (V), HD6417751F167 (V): V_DDQ = 3.0 to 3.6 V, V_DD = 1.8 V, T_a = –20 to 75°C,
C_L = 30 pF
Pin
Item
PCICLK
Clock cycle
Clock pulse width (high)
Clock pulse width (low)
Clock rise time
Clock fall time
PCIRST
Output data delay time
IDSEL
Input hold time
Input setup time
AD31–AD0
C/BE3–C/BE0
PAR
PCIFRAME
IRDY
TRDY
PCISTOP
PCILOCK
DEVSEL
PERR
Output data delay time
Tri-state drive delay time
Tri-state high-impedance
delay time
Input hold time
Input setup time
PCIREQ1/
GNTIN
PCIREQ2/
MD9
PCIREQ3/
MD10
PCIREQ4/
PCIGNT1/
REQOUT
PCIGNT4–
PCIGNT1
Output data delay time
Tri-state drive delay time
Tri-state high-impedance
delay time
Input hold time
Input setup time
SERR
INTA
Tri-state drive delay time
Tri-state high-impedance
delay time
Note: * HD6417751F167 (V)
33 MHz
Symbol Min
Max
t_PCICYC
t_PCIHIGH
t_PCILOW
t_PCIr
t_PCIf
t_PCIVAL
t_PCIH
t_PCISU
t_PCIVAL
t_PCION
t_PCIOFF
30
—
11
—
11
—
—
4
—
4
—
10
1
—
3.0 (3.5*) —
—
10
—
10
—
12
t_PCIH
t_PCISU
1
—
3.0 (3.5*) —
t_PCIVAL
t_PCION
t_PCIOFF
t_PCIH
t_PCISU
—
10
—
10
—
12
1
—
3.0 (3.5*) —
t_PCION
—
10
t_PCIOFF
—
12
66 MHz
Min
Max Unit Figure
15
30 ns 23.70
6
—
ns 23.70
6
—
ns 23.70
—
1.5 ns 23.70
—
1.5 ns 23.70
—
10 ns 23.71
1
—
ns 23.72
3.0 (3.5*) —
ns 23.72
—
10 ns 23.71
—
10 ns 23.71
—
12 ns 23.71
1
—
3.0 (3.5*) —
ns 23.72
ns 23.72
—
10 ns 23.71
—
10 ns 23.71
12 ns 23.71
1
—
3.0 (3.5*) —
ns 23.72
ns 23.72
—
10 ns 23.71
—
12 ns 23.71
Rev.4.00 Oct. 10, 2008 Page 1070 of 1122
REJ09B0370-0400