HD6417751RBP240V Datasheet, PDF (372/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

10. Clock Oscillation Circuits
10.2.2 CPG Pin Configuration
Table 10.1 shows the CPG pins and their functions.
Table 10.1 CPG Pins
Pin Name
Abbreviation I/O
Function
Mode control pins MD0
Input
Set clock operating mode
MD1
MD2
Crystal I/O pins
(clock input pins)
XTAL
EXTAL
Output
Input
Connects crystal resonator
Connects crystal resonator, or used as
external clock input pin
MD8
Input
Selects use/non-use of crystal resonator
When MD8 = 0, external clock is input from
EXTAL
When MD8 = 1, crystal resonator is
connected directly to EXTAL and XTAL
Clock output pin
CKIO
Output
Used as external clock output pin
Level can also be fixed
CKIO enable pin
CKE
Output
0 when CKIO output clock is unstable and in
case of synchronous DRAM self-refreshing*
Note: * Set to 1 in a power-on reset.
For details of synchronous DRAM self-refreshing, see section 13.3.5, Synchronous
DRAM Interface.
10.2.3 CPG Register Configuration
Table 10.2 shows the CPG register configuration.
Table 10.2 CPG Register
Name
Frequency control
register
Abbreviation R/W
FRQCR
R/W
Area 7
Initial Value P4 Address Address
Access
Size
Undefined H’FFC00000 H’1FC00000 16
Rev.4.00 Oct. 10, 2008 Page 272 of 1122
REJ09B0370-0400