HD6417751RBP240V Datasheet, PDF (155/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

2. Programming Model
Programming Note: After a reset, the values of FPR0_BANK0–FPR15_BANK0 and
FPR0_BANK1–FPR15_BANK1 are undefined.
2.2.4 Control Registers
Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000
00XX 1111 00XX (X = undefined))
31 30 29 28 27
16 15 14
10 9 8 7
43210
— MD RB BL
—
FD
—
MQ
IMASK
— ST
Note: —: Reserved. These bits are always read as 0, and should only be written with 0.
• MD: Processor mode
MD = 0: User mode (some instructions cannot be executed, and some resources cannot be
accessed)
MD = 1: Privileged mode
• RB: General register specification bit in privileged mode (set to 1 by a reset, exception, or
interrupt)
RB = 0: R0_BANK0–R7_BANK0 are accessed as general registers R0–R7. (R0_BANK1–
R7_BANK1 can be accessed using LDC/STC instructions.)
RB = 1: R0_BANK1–R7_BANK1 are accessed as general registers R0–R7. (R0_BANK0–
R7_BANK0 can be accessed using LDC/STC instructions.)
• BL: Exception/interrupt block bit (set to 1 by a reset, exception, or interrupt)
BL = 1: Interrupt requests are masked. If a general exception other than a user break occurs
while BL = 1, the processor switches to the reset state.
• FD: FPU disable bit (cleared to 0 by a reset)
FD = 1: An FPU instruction causes a general FPU disable exception, and if the FPU instruction
is in a delay slot, a slot FPU disable exception is generated. (FPU instructions: H'F***
instructions, LDC(.L)/STS(.L) instructions for FPUL/FPSCR)
• M, Q: Used by the DIV0S, DIV0U, and DIV1 instructions.
• IMASK: Interrupt mask level
Interrupts of a lower level than IMASK are masked. IMASK does not change when an
interrupt is generated.
• S: Specifies a saturation operation for a MAC instruction.
Rev.4.00 Oct. 10, 2008 Page 55 of 1122
REJ09B0370-0400