HD6417751RBP240V Datasheet, PDF (603/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. Direct Memory Access Controller (DMAC)
Table 14.3 DMAC Registers
Chan-
nel Name
Abbre-
viation
Read/
Area 7
Write Initial Value P4 Address Address
Access
Size
0
DMA source
SAR0
R/W Undefined H'FFA00000 H'1FA00000 32
address register 0
DMA destination ^DAR0
address register 0
R/W Undefined H'FFA00004 H'1FA00004 32
DMA transfer
count register 0
DMATCR0 _{R/W Undefined H'FFA00008 H'1FA00008 32}
DMA channel
CHCR0
control register 0
R/W* H'00000000 H'FFA0000C H'1FA0000C 32
1
DMA source
SAR1
R/W Undefined H'FFA00010 H'1FA00010 32
address register 1
DMA destination ^DAR1
address register 1
R/W Undefined H'FFA00014 H'1FA00014 32
DMA transfer
count register 1
DMATCR1 _{R/W Undefined H'FFA00018 H'1FA00018 32}
DMA channel
CHCR1
control register 1
R/W* H'00000000 ^H'FFA0001C H'1FA0001C 32
2
DMA source
SAR2
R/W _Undefined H'FFA00020 _{H'1FA00020 32}
address register 2
DMA destination ^DAR2
address register 2
R/W _Undefined H'FFA00024 _{H'1FA00024 32}
DMA transfer
count register 2
DMATCR2 R/W Undefined H'FFA00028 H'1FA00028 32
DMA channel
CHCR2 R/W* H'00000000 H'FFA0002C H'1FA0002C 32
control register 2
3
DMA source
SAR3
R/W Undefined H'FFA00030 H'1FA00030 32
address register 3
DMA destination DAR3
address register 3
R/W Undefined H'FFA00034 H'1FA00034 32
DMA transfer
count register 3
DMATCR3 R/W Undefined H'FFA00038 H'1FA00038 32
DMA channel
CHCR3 R/W* H'00000000 H'FFA0003C H'1FA0003C 32
control register 3
Com- DMA operation
mon register
DMAOR R/W* H'00000000 H'FFA00040 H'1FA00040 32
Notes: Longword access should be used for all control registers. If a different access width is
used, reads will return all 0s and writes will not be possible.
* Bit 1 of CHCR0–CHCR3 and bits 2 and 1 of DMAOR can only be written with 0 after
being read as 1, to clear the flags.
Rev.4.00 Oct. 10, 2008 Page 503 of 1122
REJ09B0370-0400