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HD6417751RBP240V Datasheet, PDF (249/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents
5. Exceptions
(3) H-UDI Reset
• Source: SDIR.TI3–TI0 = B'0110 (negation) or B'0111 (assertion)
• Transition address: H'A000 0000
• Transition operations:
Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A000 0000.
In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,
RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (IMASK)
are set to B'1111.
CPU and on-chip peripheral module initialization is performed. For details, see the register
descriptions in the relevant sections.
H-UDI_reset()
{
EXPEVT = H'00000000;
VBR = H'00000000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.IMASK = B'1111;
SR.FD = 0;
Initialize_CPU();
Initialize_Module(PowerOn);
PC = H'A0000000;
}
Rev.4.00 Oct. 10, 2008 Page 149 of 1122
REJ09B0370-0400