HD6417751RBP240V Datasheet, PDF (949/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

22. PCI Controller (PCIC)
22.1.3 Pin Configuration
Table 22.1 shows the configuration of I/O pins of the PCIC.
Table 22.1 Pin Configuration
No. Pin Name
PCI
Standard
Signal
Name Function
I/O Status
in Operating Modes
I/O Pull-up
Host
Non-host
Type Resistor*¹ Master Target Master Target Remarks
1 PCICLK CLK
PCI input clock
in
(33 MHz/66 MHz)
I
I
I
I
2 PCIRST —
Reset output
out
O
O
—
—
3 AD31 to AD[31:0] Address/data
t/s
AD0
I/O
I/O
I/O
I/O Low level
output at
reset
4 C/BE3 to C/BE[3:0] Command/byte
t/s
C/BE0
enable
O
I
O
I Low level
output at
reset
5 PAR
PAR
Parity
t/s
I/O
I/O
I/O
I/O Low level
output at
reset
6 PCIFRAME FRAME Bus cycle
s/t/s Yes
O
I
O
I
7 IRDY
IRDY
Initiator ready
s/t/s Yes
O
I
O
I
8 TRDY
TRDY Target ready
s/t/s Yes
I
O
I
O
9 PCISTOP STOP Transaction stop s/t/s Yes
I
O
I
O
10 PCILOCK LOCK Exclusive access s/t/s Yes
O
I
O
I
control
11 DEVSEL DEVSEL Device select
s/t/s Yes
I
O
I
O
12 PCIREQ1/ REQ1 Bus request
t/s
Yes
I
I
—
—
GNTIN
(host function)
GNT
Bus grant
t/s
Yes
—
—
I
13 PCIGNT1/ GNT1 Bus grant
t/s
No
REQOUT
(host function)
O
O
—
—
REQ
Bus request
t/s
No
—
—
O
14 PERR
PERR Parity error
s/t/s Yes
I/O
O
I/O
O
15 SERR
SERR System error
o/d
Yes
O
O
O
O
16 INTA
INTA
Interrupt (async) o/d
Yes
—
—
O
O
Rev.4.00 Oct. 10, 2008 Page 849 of 1122
REJ09B0370-0400