HD6417751RBP240V Datasheet, PDF (1190/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

C. Mode Pin Settings
Table C.2 Clock Operating Modes (SH7751R)
Clock
Operating
Mode
External
Pin Combination
MD2 MD1 MD0
PLL1
CPU
PLL2 Clock
Frequency
(vs. Input Clock)
Bus Peripheral
Clock Module Clock
FRQCR
Initial Value
0
0
0
0
On (×12) On 12
3
3
H'0E1A
1
1
On (×12) On 12
3/2
3/2
H'0E2C
2
1
0
On (×6) On 6
2
1
H'0E13
3
1
On (×12) On 12
4
2
H'0E13
4
1
0
0
On (×6) On 6
3
3/2
H'0E0A
5
1
On (×12) On 12
6
3
H'0E0A
6
1
0
OFF (×6) OFF 1
1/2
1/2
H'0808
Notes: 1. The multiplication factor of PLL1 is solely determined by the clock operating mode.
2. For the ranges input clock frequency, see the description of the EXTAL clock input
frequency (f ) and the CKIO clock output (f ) in section 23.3.1, Clock and Control
EX
OP
Signal Timing.
Table C.3 Area 0 Memory Map and Bus Width
MD6
0
1
Pin Value
MD4
MD3
0
0
1
1
0
1
0
0
1
1
0
1
Memory Type
Reserved (Cannot be used)
Reserved (Cannot be used)
Reserved (Cannot be used)
MPX interface
Reserved (Cannot be used)
SRAM interface
SRAM interface
SRAM interface
Bus Width
Reserved (Cannot be used)
Reserved (Cannot be used)
Reserved (Cannot be used)
32 bits
Reserved (Cannot be used)
8 bits
16 bits
32 bits
Table C.4 Endian
Pin Value
MD5
0
1
Endian
Big endian
Little endian
Rev.4.00 Oct. 10, 2008 Page 1090 of 1122
REJ09B0370-0400