HD6417751RBP240V Datasheet, PDF (520/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

13. Bus State Controller (BSC)
CKIO
Address
Tpc Tr1 Tr2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2
Row
c1
c2
c8
CSn
RD/WR
RAS
CASn
D31–D0
(read)
D31–D0
(write)
d1
d2
d1
d2
d8
d8
BS
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.19 (1) DRAM Burst Bus Cycle, RAS Down Mode Start
(Fast Page Mode, RCD = 0, AnW = 0)
Rev.4.00 Oct. 10, 2008 Page 420 of 1122
REJ09B0370-0400