HD6417751RBP240V Datasheet, PDF (53/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Item
Page
23.3.3 Bus Timing 1052
Figure 23.50 PCMCIA
Memory Bus Cycle
(1) TED [2:0] = 000,
TEH [2:0] = 000, No
Wait
(2) TED [2:0] = 001,
TEH [2:0] = 001, One
Internal Wait + One
External Wait
23.3.4 Peripheral
1061,
Module Signal Timing 1062
Table 23.23 Peripheral
Module Signal Timing
(1)
Table 23.24 Peripheral 1063,
Module Signal Timing 1064
(2)
Revision (See Manual for Details)
Figure amended
Tpcm0 Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w
CKIO
t_AD
t_AD
A25–A0
CExx
REG (WE0)
RD/WR
t_CSD
t_RWD
t_CSD
t_RWD
RD
D15–D0
(read)
t_RSD
t_WED1
t_RSD
t_RSD
t_RDS
t_RDH
t_WEDF
Table and notes amended
Module Item
HD6417751
RBP240 (V)
HD6417751
RBG240 (V)
HD6417751
RBP200 (V)
HD6417751
RBG200 (V)
HD6417751
RF240 (V)
HD6417751
RF200 (V)
*²
*²
*²
*²
Symbol Min Max Min Max Min Max Min Max Unit
Figure Notes
Notes: 1. Pcyc: P clock cycles
2. V_DDQ = 3.0 to 3.6 V, V_DD = 1.5 V, T_a = –20 to +75°C,
C = 30 pF, PLL2 on
L
Table and notes amended
HD6417751VF133 deleted
HD6417751BP167
HD6417751F167 (V)
Module Item
Symbol
Min
*2
Max
Unit Figure Notes
Notes: 1. Pcyc: P clock cycles
2. V = 3.0 to 3.6 V, V = 1.8 V , T = –20 to 75°C,
DDQ
DD
a
C_L = 30 pF, PLL2 on
Rev.4.00 Oct. 10, 2008 Page li of xcviii
REJ09B0370-0400