HD6417751RBP240V Datasheet, PDF (51/1226 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Item
Page
23.3.3 Bus Timing 1024
Figure 23.23
Synchronous DRAM
Normal Read Bus Cycle:
ACT + READ
Commands, Burst
(RASD = 1, RCD [1:0] =
01, CAS Latency = 3)
Figure 23.24
1025
Synchronous DRAM
Normal Read Bus Cycle:
PRE + ACT + READ
Commands, Burst
(RASD = 1, RCD [1:0] =
01, TPC [2:0] = 001,
CAS Latency = 3)
Figure 23.25
1026
Synchronous DRAM
Normal Read Bus Cycle:
READ Command, Burst
(RASD = 1, CAS
Latency = 3)
Figure 23.28
1029
Synchronous DRAM
Normal Write Bus Cycle:
ACT + WRITE
Commands, Burst
(RASD=1, RCD [1:0] =
01, TRWL [2:0] = 010)
Figure 23.29
1030
Synchronous DRAM
Normal Write Bus Cycle:
PRE + ACT + WRITE
Commands, Burst
(RASD = 1, RCD [1:0] =
01, TPC [2:0] = 001,
TRWL [2:0] = 010)
Figure 23.30
1031
Synchronous DRAM
Normal Write Bus Cycle:
WRITE Command,
Burst (RASD = 1, TRWL
[2:0] = 010)
Revision (See Manual for Details)
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Rev.4.00 Oct. 10, 2008 Page xlix of xcviii
REJ09B0370-0400