PIC18CXX2_13 Datasheet, PDF (9/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
FIGURE 1-2:
PIC18C4X2 BLOCK DIAGRAM
Data Bus<8>
21
21
Address Latch
Program Memory
(up to 2M Bytes)
Data Latch
16
21 ^{Table Pointer <2>}
88
8
inc/dec logic
20
PCLATU PCLATH
PCU PCH PCL
Program Counter
31 Level Stack
Data Latch
Data RAM
(up to 4K
address reach)
Address Latch
(2)
12
Address<12>
4
BSR
12
FSR0
FSR1
FSR2
4
Bank0, F
12
Table Latch
8
ROM Latch
inc/dec
Decode
logic
OSC2/CLKO
OSC1/CLKI
T1OSI
T1OSO
Instruction
Decode &
Control
Timing
Generation
4X PLL
Precision
Voltage
Reference
Instruction
Register
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
8
PRODH PRODL
3
8 x 8 Multiply
8
BIT OP WREG
8
8
8
8
ALU<8>
8
MCLR VDD, VSS
PORTA
PORTB
PORTC
PORTD
PORTE
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RA6
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2⁽¹⁾
RB7:RB4
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2⁽¹⁾
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
Timer0
Timer1
Timer2
Timer3
A/D Converter
CCP1
CCP2
Master
Synchronous
Serial Port
Addressable
USART
Parallel Slave Port
Note
1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations
are device dependent.
 1999-2013 Microchip Technology Inc.
DS39026D-page 9