PIC18CXX2_13 Datasheet, PDF (133/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
14.4.2 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I²C bus is such that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address which
can address all devices. When this address is used, all
devices should, in theory, respond with an acknowl-
edge.
The general call address is one of eight addresses
reserved for specific purposes by the I²C protocol. It
consists of all 0’s with R/W = 0.
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is enabled (SSPCON2<7>
is set). Following a START bit detect, 8-bits are shifted
into the SSPSR and the address is compared against
the SSPADD. It is also compared to the general call
address and fixed in hardware.
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit),
the SSPIF interrupt flag bit is set.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit address mode, then the second
half of the address is not necessary, the UA bit will not
be set, and the slave will begin receiving data after the
Acknowledge (Figure 14-12).
FIGURE 14-12:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
SDA
General Call Address
Address is compared to General Call Address
after ACK, set interrupt
R/W = 0
Receiving Data
ACK
ACK _{D7 D6 D5 D4 D3 D2 D1 D0}
SCL
SSPIF
S
1 2 34 5 6 78 91 2 34 5 6 78 9
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
Cleared in software
SSPBUF is read
'0'
GCEN (SSPCON2<7>)
'1'
14.4.3 MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET or when the MSSP module is
disabled. Control of the I²C bus may be taken when the
P bit is set, or the bus is idle, with both the S and P bits
clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP interrupt, if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge Transmit
• Repeated START
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DS39026D-page 133