PIC18CXX2_13 Datasheet, PDF (257/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
FIGURE 21-17:
I²C BUS DATA TIMING
103
100
SCL
90
106
91
SDA
In
109
SDA
Out
Note: Refer to Figure 21-4 for load conditions.
101
107
109
102
92
110
TABLE 21-16: I²C BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100
THIGH
Clock high time
100 kHz mode
4.0
—
s PIC18CXXX must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
s PIC18CXXX must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
—
101
TLOW
Clock low time
100 kHz mode
4.7
—
s PIC18CXXX must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
s PIC18CXXX must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
—
102
TR
SDA and SCL rise
time
100 kHz mode
400 kHz mode
—
20 + 0.1CB
1000
300
ns
ns CB is specified to be from
10 to 400 pF
103
TF
SDA and SCL fall time 100 kHz mode
—
300
ns
400 kHz mode 20 + 0.1CB 300
ns CB is specified to be from
10 to 400 pF
90
TSU:STA START condition
100 kHz mode
4.7
setup time
400 kHz mode
0.6
—
s Only relevant for Repeated
—
s ^{START condition}
91
THD:STA START condition hold 100 kHz mode
4.0
time
400 kHz mode
0.6
—
s After this period the first clock
—
s ^{pulse is generated}
106
THD:DAT Data input hold time 100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
107
TSU:DAT Data input setup time 100 kHz mode
250
—
ns (Note 2)
400 kHz mode
100
—
ns
92
TSU:STO STOP condition setup 100 kHz mode
4.7
time
400 kHz mode
0.6
—
s
—
s
109
TAA
Output valid from
clock
100 kHz mode
400 kHz mode
—
3500 ns (Note 1)
—
—
ns
110
TBUF
Bus free time
100 kHz mode
4.7
400 kHz mode
1.3
—
s Time the bus must be free before
—
s ^{a new transmission can start}
D102 CB
Bus capacitive loading
—
400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast mode I²C bus device can be used in a standard mode I²C bus system, but the requirement TSU:DAT  250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I²C bus specification) before the SCL line is
released.
 1999-2013 Microchip Technology Inc.
DS39026D-page 257