PIC18CXX2_13 Datasheet, PDF(83/304 Page) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

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PIC18CXX2_13 Datasheet, PDF (83/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

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PIC18CXX2

8.3 PORTC, TRISC and LATC

Registers

PORTC is an 8-bit wide, bi-directional port. The corre-

sponding Data Direction Register is TRISC. Setting a

TRISC bit (= 1) will make the corresponding PORTC

pin an input (i.e., put the corresponding output driver in

a Hi-Impedance mode). Clearing a TRISC bit (= 0) will

make the corresponding PORTC pin an output (i.e., put

the contents of the output latch on the selected pin).

Note: On a Power-on Reset, these pins are con-

figured as digital inputs.

The Data Latch register (LATC) is also memory

mapped. Read-modify-write operations on the LATC

register reads and writes the latched output value for

PORTC.

PORTC is multiplexed with several peripheral functions

(Table 8-5). PORTC pins have Schmitt Trigger input

buffers.

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTC pin. Some

peripherals override the TRIS bit to make a pin an out-

put, while other peripherals override the TRIS bit to make

a pin an input. The user should refer to the correspond-

ing peripheral section for the correct TRIS bit settings.

The pin override value is not loaded into the TRIS reg-

ister. This allows read-modify-write of the TRIS register,

without concern due to peripheral overrides.

RC1 is normally configured by the configuration bit

CCP2MX as the default peripheral pin for the CCP2

module (default/erased state, CCP2MX = â1â).

EXAMPLE 8-3: INITIALIZING PORTC

CLRF PORTC

CLRF LATC

MOVLW 0xCF

MOVWF TRISC

; Initialize PORTC by

; clearing output

; data latches

; Alternate method

; to clear output

; data latches

; Value used to

; initialize data

; direction

; Set RC<3:0> as inputs

; RC<5:4> as outputs

; RC<7:6> as inputs

FIGURE 8-7:

PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)

Port/Peripheral Select(2)

VDD

Peripheral Data Out

RD LATC

0

Data Latch

Data Bus

WR LATC or

WR PORTC

DQ

CK Q

1

P

DDR Latch

DQ

WR TRISC

CK Q

N

RD TRISC

Peripheral Output

Enable(3)

RD PORTC

Peripheral Data In

VSS

QD

EN

Note 1: I/O pins have diode protection to VDD and VSS.

2: Port/Peripheral select signal selects between port data (input) and peripheral output.

3: Peripheral Output Enable is only active if peripheral select is active.

I/O pin(1)

Schmitt

Trigger

ï£ 1999-2013 Microchip Technology Inc.

DS39026D-page 83

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