PIC18CXX2_13 Datasheet, PDF (195/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
ANDWF
AND WREG with f
Syntax:
Operands:
Operation:
[ label ] ANDWF f [,d [,a]
0  f  255
d [0,1]
a [0,1]
(WREG) .AND. (f)  dest
Status Affected:
Encoding:
Description:
N,Z
0001 01da ffff ffff
The contents of WREG are AND’ed
with register 'f'. If 'd' is 0, the result
is stored in WREG. If 'd' is 1, the
result is stored back in register 'f'
(default). If ‘a’ is 0, the Access
Bank will be selected. If ‘a’ is 1, the
BSR will not be overridden
(default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register 'f'
Q3
Process
Data
Q4
Write to
destination
Example:
ANDWF
Before Instruction
WREG = 0x17
REG
= 0xC2
After Instruction
WREG
REG
= 0x02
= 0xC2
REG, 0, 0
BC
Branch if Carry
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
[ label ] BC n
-128  n  127
if carry bit is ’1’
(PC) + 2 + 2n  PC
None
1110 0010 nnnn nnnn
If the Carry bit is ’1’, then the pro-
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Decode
Read literal
'n'
No
operation
No
operation
If No Jump:
Q1
Q2
Decode
Read literal
'n'
Q3
Process
Data
No
operation
Q3
Process
Data
Q4
Write to PC
No
operation
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Carry =
PC
=
If Carry 
PC
=
BC 5
address (HERE)
1;
address (HERE+12)
0;
address (HERE+2)
 1999-2013 Microchip Technology Inc.
DS39026D-page 195