PIC18CXX2_13 Datasheet, PDF (161/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
15.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 15.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 15-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other
RESETS
INTCON
PIR1
PIE1
IPR1
GIE/
GIEH
PSPIF⁽¹⁾
PSPIE⁽¹⁾
PSPIP⁽¹⁾
PEIE/
GIEL
ADIF
ADIE
ADIP
TMR0IE INT0IE
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF INT0IF RBIF 0000 000x 0000 000u
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x
RCREG USART Receive Register
0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Master Reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
FIGURE 15-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit ^'0'
'0'
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = '1' and bit BRGH = '0'.
 1999-2013 Microchip Technology Inc.
DS39026D-page 161