PIC18CXX2_13 Datasheet, PDF (19/304 Pages) Microchip Technology – High Performance Microcontrollers with 10-bit A/D

PIC18CXX2
2.4 External Clock Input
The EC and ECIO oscillator modes require an external
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is no oscilla-
tor start-up time required after a Power-on Reset or
after a recovery from SLEEP mode.
In the EC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
oscillator mode.
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
Clock from
Ext. System
FOSC/4
OSC1
PIC18CXXX
OSC2
The ECIO oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO oscillator mode.
FIGURE 2-6:
PLL BLOCK DIAGRAM
(from Configuration
bit Register)
HS Osc
PLL Enable
FIGURE 2-5:
EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
Clock from
Ext. System
RA6
OSC1
PIC18CXXX
I/O (OSC2)
2.5 HS/PLL
A Phase Locked Loop circuit is provided as a program-
mable option for users that want to multiply the fre-
quency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high frequency crystals.
The PLL can only be enabled when the oscillator con-
figuration bits are programmed for HS mode. If they are
programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
The PLL is one of the modes of the FOSC<2:0> config-
uration bits. The oscillator mode is specified during
device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called TPLL.
OSC2
OSC1
Crystal
Osc
Phase
Comparator
FIN
FOUT
Loop
Filter
VCO
Divide by 4
SYSCLK
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DS39026D-page 19